Non-volatile memory device

ABSTRACT

A nonvolatile memory device includes a conductive layer, a semiconductor layer extending in a first direction on the conductive layer, a first insulating layer provided between the conductive layer and the semiconductor layer, a word line extending in a second direction on the semiconductor layer, the second direction intersecting the first direction, a charge storage layer provided between the semiconductor layer and the word line, and a circuit electrically connected to the conductive layer. The circuit applies an electric potential to the conductive layer when programming data, the electric potential of the conductive layer having the same polarity as an electric potential of the word line.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromU.S. Provisional Patent Application 62/214,025 filed on Sep. 3, 2015;the entire contents of which are incorporated herein by reference.

FIELD

Embodiments are generally related to a non-volatile memory device.

BACKGROUND

A nonvolatile memory device such as a NAND type memory device comprisesa memory cell transistor including a semiconductor layer, a chargestorage layer, and a word line. The charge storage layer is provided,with an insulating layer interposed, between the semiconductor layer andthe word line. When programming information to the memory celltransistor, electric charges are injected from the semiconductor layerinto the charge storage layer by applying a prescribed bias between thesemiconductor layer and the word line. On the other hand, when erasingthe information stored in the memory cell transistor, the reverse biasopposite to the programming bias is applied between the semiconductorlayer and the word line in order to remove the electric charges from thecharge storage layer. However, such programming and erasing of theinformation damages the insulating layer between the semiconductor layerand the charge storage layer and causes the data retentioncharacteristics to degrade. Also, the life of the semiconductor memorydevice is limited by the number of times of programming and erasing.

For example, one word line is shared by multiple memory celltransistors. The control circuit applies the bias via the word line notonly to the memory cell transistor that is selected for programming theinformation but also to the memory cell transistors that are unselected.Thus, it is desirable for the NAND type memory device to have astructure capable of reducing the bias applied to the unselected memorycell transistors, thereby suppressing the damage of the insulatinglayer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are schematic views showing a nonvolatile memory deviceaccording to a first embodiment;

FIGS. 2A, 2B, 2C and 2D are schematic cross-sectional views showingoperations of the memory cell array according to the first embodiment;

FIGS. 3A, 3B, 3C and 3D are graphs showing characteristics of thenonvolatile memory device according to the first embodiment;

FIGS. 4A, 4B, 4C and 4D are schematic cross-sectional views showingoperations of a memory cell array according to a variation of the firstembodiment;

FIGS. 5A, 5B, 6A and 6B are schematic cross-sectional views showingoperations of memory cell arrays according to other variations of thefirst embodiment;

FIG. 7 is a schematic view showing a nonvolatile memory device accordingto a second embodiment;

FIGS. 8A and 8B are schematic cross-sectional views showing operationsof the memory cell array according to the second embodiment;

FIGS. 9A and 9B are schematic views showing a memory cell arrayaccording to a third embodiment;

FIGS. 10A, 10B, 11A, 11B, 11C, 12A, 12B, 13A, 13B, 13C, 13D, 13E, 14A,14B, 14C, 14D, 15A, 15B, 15C, 15D, 15E, 16A, 16B, 16C, 16D, 16E, 17A,17B, 17C, 17D, 17E, 18A, 18B, 18C, 18D, 18E, 19A, 19B, 19C, 19D, 19E,20A, 20B, 20C, 20D, 20E, 21A, 21B, 21C, 21D, 21E, 22A, 22B, 22C, 22D and22E are schematic cross-sectional views showing a manufacturingprocesses of the memory cell array according to the third embodiment;

FIGS. 23A, 23B, 23C, 23D and 23E are schematic views showing the memorycell array according to the third embodiment;

FIGS. 24A, 24B, 24C, 24D and 24E are schematic views showing a memorycell array according to a variation of the third embodiment;

FIGS. 25A, 25B, 25C, 25D and 25E are schematic views showing a memorycell array according to another variation of the third embodiment; and

FIGS. 26A, 26B, 26C and 26D are schematic views showing characteristicsof the nonvolatile memory device according to the first embodiment.

DETAILED DESCRIPTION

According to one embodiment, a nonvolatile memory device includes aconductive layer, a semiconductor layer extending in a first directionon the conductive layer, a first insulating layer provided between theconductive layer and the semiconductor layer, a word line extending in asecond direction on the semiconductor layer, the second directionintersecting the first direction, a charge storage layer providedbetween the semiconductor layer and the word line, and a circuitelectrically connected to the conductive layer. The circuit applies anelectric potential to the conductive layer when programming data, theelectric potential of the conductive layer having the same polarity asan electric potential of the word line.

Embodiments will now be described with reference to the drawings. Thesame portions inside the drawings are marked with the same numerals; adetailed description is omitted as appropriate; and the differentportions are described. The drawings are schematic or conceptual; andthe relationships between the thicknesses and widths of portions, theproportions of sizes between portions, etc., are not necessarily thesame as the actual values thereof. The dimensions and/or the proportionsmay be illustrated differently between the drawings, even in the casewhere the same portion is illustrated.

There are cases where the dispositions of the components are describedusing the directions of XYZ axes shown in the drawings. The X-axis, theY-axis, and the Z-axis are orthogonal to each other. Hereinbelow, thedirections of the X-axis, the Y-axis, and the Z-axis are described as anX-direction, a Y-direction, and a Z-direction. Also, there are caseswhere the Z-direction is described as upward and the direction oppositeto the Z-direction is described as downward.

The embodiments described below are not limited to the examplesdescribed therein. Also, the components and the operations thereofdescribed in each embodiment are not unique to each embodiment and aremutually applicable if technically feasible.

First Embodiment

FIGS. 1A and 1B are schematic views showing a nonvolatile memory device1 according to a first embodiment. FIG. 1A is a block diagram showingthe configuration of the nonvolatile memory device 1. FIG. 1B is aschematic view showing a memory cell array 2 of the nonvolatile memorydevice 1.

The nonvolatile memory device 1 is, for example, a NAND EEPROM(electrically erasable programmable ROM). As shown in FIG. 1A, thenonvolatile memory device 1 includes, for example, a memory unit 12, arow decoder 13, a sense amplifier 15, a source potential supply unit 16,a substrate potential supply unit 17, a controller 18, and an interface19. The row decoder 13, the sense amplifier 15, the source potentialsupply unit 16, the substrate potential supply unit 17, the controller18, and the interface 19 each are functional blocks and are included ina so-called peripheral circuit. It is sufficient for the peripheralcircuit to include the functions of the blocks as an entirety; and it isunnecessary to include the functions in a form in which the circuitregion corresponding to each block can be discriminated.

The memory unit 12 includes, for example, multiple memory blocks MB.Each of the memory blocks MB includes the memory cell array 2 shown inFIG. 2. The memory cell array 2 includes multiple semiconductor layers20, word lines 30, and selection gates 40 d and 40 s. The semiconductorlayers 20 extend in a first direction (hereinbelow, an X-direction). Thesemiconductor layers 20 are arranged in a second direction (hereinbelow,a Y-direction). The semiconductor layers 20 are provided to be parallelto each other.

The word lines 30 extend in a direction crossing the semiconductorlayers 20. In the example, the word lines 30 extend in the Y-direction.The multiple word lines 30 are arranged in the X-direction. The wordlines 30 are provided to be parallel to each other. Charge storagelayers 21 (referring to FIG. 2A) are provided at the portions where thesemiconductor layers 20 and the word lines 30 cross. Memory celltransistors MTr are provided at the portions where the semiconductorlayers 20 and the word lines 30 cross. The memory cell transistors MTrinclude the charge storage layers 21 provided between the semiconductorlayers 20 and the word lines 30. Also, the multiple memory celltransistors MTr share one word line 30.

The selection gates 40 d and 40 s extend in directions crossing thesemiconductor layers 20. In the example, the selection gates 40 d and 40s extend in the Y-direction. The multiple word lines 30 10 are arrangedbetween the selection gate 40 d and the selection gate 40 s. Selectiontransistors STD are provided at the portions where the semiconductorlayers 20 and the selection gate 40 d cross. Selection transistors STSare provided at the portions where the semiconductor layers 20 and theselection gate 40 s cross. Multiple 15 selection transistors STD shareone selection gate 40 d. Multiple selection transistors STS share oneselection gate 40 s.

Multiple drain contacts 50 are provided on the side of the selectiongate 40 d opposite to the word lines 30. The drain contacts 50 areelectrically connected respectively to the semiconductor layers 20. Thedrain contacts 50 are electrically connected to bit lines BL (referringto FIG. 2A). In other words, the drain contacts 50 electrically connectthe semiconductor layers 20 to the bit lines BL.

A source contact 60 is provided on the side of the selection gate 40 sopposite to the word lines 30. For example, the source contact 60extends in the Y-direction and is electrically connected to the multiplesemiconductor layers 20. The source contact 60 is shared by the multiplesemiconductor layers 20. The source contact 60 electrically connects thesemiconductor layers 20 to a not-shown source line SL (referring to FIG.7).

The row decoder 13 supplies a gate potential V_(GM) to the multiplememory cell transistors MTr via the word lines 30. The row decoder 13supplies a gate potential V_(GD) to the multiple selection transistorsSTD via the selection gate 40 d. Also, the row decoder 13 supplies agate potential V_(GS) to the multiple selection transistors STS via theselection gate 40 s.

The sense amplifier 15 is electrically connected to the semiconductorlayers 20 via the bit lines BL and the drain contacts 50. The sourcepotential supply unit 16 is electrically connected to the semiconductorlayers 20 via the source line SL and the source contact 60. Thesubstrate potential supply unit 17 is electrically connected to anot-shown substrate 10 (referring to FIG. 2A). The sense amplifier 15and the source potential supply unit 16 maintain the semiconductorlayers 20 at a prescribed potential. Namely, the sense amplifier 15 andthe source potential supply unit 16 supply a channel potential Vch tothe memory cell transistors MTr.

For example, the controller 18 receives a command sent from the outsidevia the interface 19 and performs the programming of data, the readingof data, and the erasing of data to and from the memory cell transistorsMTr. Specifically, the controller 18 performs the programming of thedata, the reading of the data, and the erasing of the data bycontrolling the gate potential V_(GM) and the channel potential Vch ofthe memory cell transistors MTr via the row decoder 13, the senseamplifier 15, the source potential supply unit 16, and the substratepotential supply unit 17.

FIGS. 2A to 2D are schematic cross-sectional views showing operations ofthe memory cell array 2. FIGS. 2A to 2D are cross-sectional views alongline 1B-1B shown in FIG. 1B. In FIGS. 2A to 2D, the insulating layersthat are provided to be higher than the semiconductor layer 20 are notshown.

As shown in FIGS. 2A to 2D, the memory cell array 2 is provided on thesubstrate 10. The memory cell array 2 further includes an insulatinglayer 70 between the substrate 10 and the semiconductor layer 20. Theinsulating layer 70 electrically insulates the semiconductor layer 20from the substrate 10. The word lines 30 and the selection gates 40 dand 40 s are provided above the semiconductor layer 20.

The substrate 10 is, for example, a silicon substrate. The insulatinglayer 70 is, for example, a silicon oxide layer. The semiconductor layer20 is, for example, a silicon layer. For example, the nonvolatile memorydevice 1 is made using a wafer having an SOI (Silicon on Insulator)structure.

The memory cell transistor MTr includes a portion of the semiconductorlayer 20, the charge storage layer 21, and a portion of the word line30. The charge storage layer 21 is provided between the semiconductorlayer 20 and the word line 30. The portion of the semiconductor layer 20functions as a channel of the memory cell transistor MTr; and theportion of the word line 30 functions as a control gate of the memorycell transistor MTr. The memory cell transistor MTr further includes aninsulating layer 27 and an insulating layer 29. The insulating layer 27is provided between the semiconductor layer 20 and the charge storagelayer 21; and the insulating layer 29 is provided between the chargestorage layer 21 and the word line 30. For example, the insulating layer27 functions as a tunneling insulating layer. For example, theinsulating layer 29 functions as a blocking insulating layer.

The selection transistor STD includes a portion of the semiconductorlayer 20, a conductive layer 23, and a portion of the selection gate 40d. The conductive layer 23 is provided between the semiconductor layer20 and the selection gate 40 d. The conductive layer 23 includes, forexample, the same material as the charge storage layer 21. The selectiontransistor STD further includes the insulating layer 27 and theinsulating layer 29. The insulating layer 27 is provided between thesemiconductor layer 20 and the conductive layer 23; and the insulatinglayer 29 is provided between the conductive layer 23 and the selectiongate 40 d. The conductive layer 23 is electrically connected to theselection gate 40 d via a connecting portion 24 extending through theinsulating layer 29. The portion of the semiconductor layer 20 functionsas a channel of the selection transistor STD; and the conductive layer23 and the portion of the selection gate 40 d function as a gateelectrode of the selection transistor STD. The insulating layer 27functions as a gate insulation layer of the selection transistor STD.

The conductive layers 23 are not necessarily electrically connected tothe selection gates 40 d and 40 s. For example, the conductive layers 23may be electrically isolated from the selection gates 40 d and 40 s ifthe threshold voltages of the selection transistors STD and STS are in aprescribed range. Thereby, the process of forming the connectingportions 24 can be omitted.

The selection transistor STS includes a portion of the semiconductorlayer 20, the conductive layer 23, and a portion of the selection gate40 s. The conductive layer 23 is provided between the semiconductorlayer 20 and the selection gate 40 s. The selection transistor STSfurther includes the insulating layer 27 and the insulating layer 29.The insulating layer 27 is provided between the semiconductor layer 20and the conductive layer 23; and the insulating layer 29 is providedbetween the conductive layer 23 and the selection gate 40 s. Theconductive layer 23 is electrically connected to the selection gate 40 svia a connecting portion extending through the insulating layer 29. Theportion of the semiconductor layer 20 functions as a channel of theselection transistor STS; and the conductive layer 23 and the portion ofthe selection gate 40 s function as a gate electrode of the selectiontransistor STS. The insulating layer 27 functions as a gate insulationlayer of the selection transistor STS.

The semiconductor layer 20 includes a contact portion 20 d and a contactportion 20 s. The drain contact 50 is electrically connected to thecontact portion 20 d. The source contact 60 is electrically connected tothe contact portion 20 s. The contact portions 20 d and 20 s are, forexample, regions of the semiconductor layer 20 doped with an n-typeimpurity having a high concentration.

The memory cell array 2 includes, for example, multiple memory strings.One memory string includes, between the drain contact 50 and the sourcecontact 60, the multiple memory cell transistors MTr and the selectiontransistors STD and STS that share one semiconductor layer 20. The draincontact 50 is provided on the drain side of the selection transistorSTD; and the memory cell transistors MTr are provided on the source sideof the selection transistor STD. Also, the memory cell transistors MTrare provided on the drain side of the selection transistor STS; and thesource contact 60 is provided on the source side of the selectiontransistor STS.

The semiconductor layer 20 is electrically connected to the bit line BLvia the drain contact 50. The bit line BL extends in the X-directionabove the word lines 30 and the selection gates 40 d and 40 s (referringto FIG. 7). The bit line BL is electrically connected to the senseamplifier 15. Also, the semiconductor layer 20 is electrically connectedto the source line SL via the source contact 60. The source line SL iselectrically connected to the source potential supply unit 16.

FIGS. 2A and 2B show the gate potentials V_(GM), V_(GD), and V_(GS), thepotential of the bit line BL, and the potential of the source line SLwhen programming data. FIG. 2A shows a memory string MS1; and FIG. 2Bshows a memory string MS2. The memory string MS1 includes a memory celltransistor MTrs that is selected for programming data, and memory celltransistors MTrn that are unselected. The memory string MS2 includesonly the unselected memory cell transistors MTrn. The word lines 30 andthe selection gates 40 d and 40 s are shared by the memory strings MS1and MS2.

In the description hereinbelow, the selected memory cell transistor MTrsand the unselected memory cell transistors MTrn may be discriminated; orthe two may be generally referred to as the memory cell transistor MTr.The other components also may be discriminated individually or may begenerally referred to.

For example, via the sense amplifier 15, the controller 18 selects a bitline BL1 electrically connected to the memory string MS1 and sets thepotential of the bit line BL1 to 0 (zero) V. On the other hand, via thesense amplifier 15, the controller 18 applies Vcc to a bit line BL2connected to the memory string MS2. For example, a potential of 2 V isapplied to the source line SL via the source potential supply unit 16.

Then, via the row decoder 13, the controller 18 applies Vcc to theselection gate 40 d and sets the potential of the selection gate 40 s to0 (zero) V. Further, via the row decoder 13, the controller 18 appliesVpp to the word line 30 connected to the memory cell transistor MTrs.Also, via the row decoder 13, the controller 18 applies Vpass to theother word lines 30 connected to the memory cell transistors MTrn. Here,Vcc is the power supply voltage and is, for example, 3 V. Vpp is theprogramming voltage and is, for example, 20 V. Vpass is higher than thethreshold voltage of the memory cell transistors MTrn and switches thememory cell transistors MTrn ON. Vpass is, for example, 9 V.

In the memory string MS1 shown in FIG. 2A, the gate potential V_(GD) ofa selection transistor STD1 is Vcc; and the drain potential of theselection transistor STD1 is 0 V. Accordingly, the selection transistorSTD1 is switched to the ON state. On the other hand, the gate potentialV_(GS) of a selection transistor STS1 is 0 V; and the source potentialof the selection transistor STS1 is 2 V. Therefore, the selectiontransistor STS1 is switched to the OFF state. Also, the gate potentialsof the memory cell transistors MTrs and MTrn are higher than thethreshold voltage; and the memory cell transistors MTrs and MTrn areswitched to the ON state. As a result, a channel potential Vch1 of thememory cell transistors MTr is 0 V which is the same as that of the bitline BL1. Then, by the programming voltage Vpp applied to thegate-channel of the memory cell transistor MTrs, charge is injected froma semiconductor layer 20 a into the charge storage layer 21; and thedata is programmed to the memory cell transistor MTrs.

In contrast, in the memory string MS2 shown in FIG. 2B, Vcc is appliedto the drain side of a selection transistor STD2 via the bit line BL2.The selection transistor STD2 shares the selection gate 40 d with theselection transistor STD1. Accordingly, the gate potential V_(GD) isVcc. Therefore, the selection transistor STD2 is switched to the OFFstate. On the other hand, a selection transistor STS2 shares theselection gate 40 s with the selection transistor STS1; and the gatepotential V_(GS) of the selection transistor STS2 is 0 V. A potential of2 V is applied to the source side of the selection transistor STS2 viathe source line SL. Therefore, the selection transistor STS2 is switchedto the OFF state. As a result, a channel potential Vch2 of the memorycell transistors MTr is a floating potential.

The channel potential Vch2 of the memory string MS2 is dependent on thepotentials of the word line 30 and the substrate 10 via a capacitivecoupling between a semiconductor layer 20 b and the word line 30 and acapacitive coupling between the substrate 10 and the semiconductor layer20. In the embodiment, for example, the controller 18 applies a biasVsub to the substrate 10 via the substrate potential supply unit 17.Vsub is, for example, 3 to 9 V. Accordingly, the channel potential Vch2is pushed upward to the positive side. As a result, in the memory stringMS2, it is possible to set the potential difference between the wordline 30 and the channel of the memory cell transistor MTrn to be small;and, for example, the damage of the tunneling insulating layer may besuppressed.

For example, when programming data, the programming voltage Vpp isapplied to the control gates of the unselected memory cell transistorsMTrn that share the word line 30 with the selected memory celltransistor MTrs. In contrast, by increasing the potential of thesubstrate 10 and increasing the channel potential Vch2 of the unselectedmemory cell transistors MTrn, the potential difference between the wordline 30 and the channel thereof can be set to be smaller than Vpp. Inother words, by boosting the channel potential, the damage of thetunneling insulating layer of the unselected memory cell transistorsMTrn may be suppressed. As a result, the data retention characteristicsof the memory cell transistors MTr are improved; and it is possible torealize a longer life of the nonvolatile memory device 1.

FIG. 2C shows the gate potentials V_(GM), V_(GD), and V_(GS), thepotential of the bit line BL, and the potential of the source line SLwhen erasing data. For example, the data erasure is executedcollectively for each memory block MB.

As shown in FIG. 2C, the controller 18 applies an erasing voltage Veravia the source potential supply unit 16 to the source lines SL of thememory block MB for which the data is to be erased. On the other hand,the controller 18 sets the potential of the bit line BL to the floatingpotential via the sense amplifier 15. Also, via the row decoder, thecontroller 18 sets the potentials of the selection gates 40 d and 40 sto the floating potential and sets the potential of each word line 30 to0 V.

By the potential setting recited above, the gate potential V_(GD) of theselection transistor STD is set to the floating potential; and theselection transistor STD is switched to the OFF state. Also, the gatepotential V_(GS) of the selection transistor STS is set to the floatingpotential; and the source potential is Vera. Therefore, the selectiontransistor STS is switched to the ON state; and the channel potentialVch of the memory cell transistors MTr is set to Vera. As a result, Verais applied between the word line 30 and the channel of the memory celltransistor MTr; and the electric charges are removed from the chargestorage layer 21 into the semiconductor layer 20. Thereby, the data thatis stored in the memory cell transistors MTr is erased.

When erasing data, it is favorable for the controller 18 to apply thepotential of Vera to the substrate 10 via the substrate potential supplyunit. Thereby, the substrate 10 and the semiconductor layer 20 are setto the same potential; and the damage of the insulating layer 70occurring due to the electric field can be avoided.

FIG. 2D shows the gate potentials V_(GM), V_(GD), and V_(GS), thepotential of the bit line BL, and the potential of the source line SLwhen reading data. FIG. 2D is a cross-sectional view of a memory stringMS including the memory cell transistor MTrs that is selected forreading the data.

As shown in FIG. 2D, the controller 18 applies Vcc to the selectiongates 40 d and 40 s via the row decoder 13. Also, via the row decoder13, the controller 18 applies Vdata to the word line 30 connected to theselected memory cell transistor MTrs and applies Vread to the word lines30 connected to the unselected memory cell transistors MTrn. Then, thecontroller 18 applies Vbit to the bit line BL via the sense amplifier 15and sets the potential of the source line SL to 0 V via the sourcepotential supply unit 16. Here, Vread is a voltage that is higher thanthe threshold of the memory cell transistors MTr; and Vbit is, forexample, a voltage that is between 0 V and Vcc.

By the potential setting recited above, the gate potentials V_(GD) andV_(GS) of the selection transistors STD and STS are set to Vcc; and theselection transistors STD and STS are switched to the ON state. Also,the gate potential V_(GM) of the unselected memory cell transistors MTrnis Vread; and the unselected memory cell transistors MTrn are switchedto the ON state. Then, via the row decoder 13, the controller 18 sweepsVdata and uses the sense amplifier 15 to sense the flow/non-flow of achannel current flowing through the semiconductor layer 20 from the bitline BL to the source line SL. The sweep range of Vdata includes thethreshold voltage of the memory cell transistors MTr. In other words,the threshold voltage is sensed by sweeping the gate potential V_(GM) ofthe memory cell transistor MTrs. Thereby, the controller 18 can read thedata stored in the memory cell transistor MTrs.

When reading the data, for example, it is favorable for the controller18 to apply a potential of −1 V to 0 V to the substrate 10 via thesubstrate potential supply unit 17. Thereby, the channel resistance ofthe memory cell transistors MTr is reduced; and the current can beincreased while reading. In other words, the Signal to Noise ratio ofthe channel current is set to be large when sensing; and the read-outprecision of the data may be increased.

FIGS. 3A to 3D are graphs showing characteristics of the nonvolatilememory device 1 according to the first embodiment. FIGS. 3A to 3D aregraphs showing the potential Vsub of the substrate 10 and the potentialV_(Ch) of the channel in the floating state. FIG. 3A is thecharacteristics when a thickness T_(OX) in the Z-direction of theinsulating layer 70 (referring to FIG. 2A) is set to 100 nm. FIG. 3B,T_(OX) is set to 40 nm; in FIG. 3C, T_(OX) is set to 20 nm; and in FIG.3D, T_(OX) is set to 8 nm. Also, A shown in each figure illustrates thecharacteristic in the case where a thickness T_(S) in the Z-direction ofthe semiconductor layer 20 (referring to FIG. 2A) is set to 10 nm; Billustrates the characteristic in the case where the thickness T_(S) ofthe semiconductor layer 20 is set to 20 nm; and C illustrates thecharacteristic in the case where the thickness T_(S) of thesemiconductor layer 20 is set to 30 nm.

As shown in FIGS. 3A to 3D, the channel potential Vch increases as thesubstrate potential Vsub is increased. Also, the channel potential Vchincreases as the thickness T_(S) of the semiconductor layer 20 isreduced. In other words, the boost of the channel potential Vch can beincreased as the thickness T_(S) of the semiconductor layer 20 isreduced. The increase amount of the channel potential Vch increases asthe thickness T_(OX) of the insulating layer 70 is reduced. In otherwords, the boost of the channel potential Vch can be increased as thethickness T_(OX) of the insulating layer 70 is reduced.

FIGS. 4A to 4D are schematic cross-sectional views showing operations ofa memory cell array 3 according to a variation of the first embodiment.FIGS. 4A to 4D are cross-sectional views along line 1B-1B shown in FIG.1B. In FIGS. 4A to 4D, the insulating layers that are provided to behigher than the semiconductor layer 20 are not shown.

As shown in FIGS. 4A to 4D, the memory cell array 3 is provided on thesubstrate 10. The memory cell array 3 includes the memory celltransistors MTr, the selection transistor STD, and the selectiontransistor STS. The memory cell array 3 further includes the insulatinglayer 70 between the substrate 10 and the semiconductor layer 20.

The memory cell array 3 includes a contact portion 25 on the source sideof the selection transistor STS. The contact portion 25 is provided fromthe upper surface of the semiconductor layer 20 to a depth that reachesthe substrate 10. The source contact 60 is electrically connected to thecontact portion 25. The contact portion 25 is, for example, asemiconductor region doped with an n-type impurity having a highconcentration and electrically connects the semiconductor layer 20 tothe substrate 10.

FIGS. 4A and 4B show the gate potentials V_(GM), V_(GD), and V_(GS), thepotential of the bit line BL, and the potential of the source line SLwhen programming data. FIG. 4A shows the memory string MS1; and FIG. 4Bshows the memory string MS2. The memory string MS1 includes the memorycell transistor MTrs that is selected for programming data, and thememory cell transistors MTrn that are unselected. The memory string MS2includes only the unselected memory cell transistors MTrn. The wordlines 30 and the selection gates 40 d and 40 s are shared by the memorystrings MS1 and MS2.

For example, via the sense amplifier 15, the controller 18 selects thebit line BL1 electrically connected to the memory string MS1 and setsthe potential of the bit line BL1 to 0 (zero) V. Also, via the senseamplifier 15, the controller 18 applies Vcc to the bit line BL2connected to the memory string MS2. Further, for example, a potential of3 V is applied to the source line SL via the source potential supplyunit 16. In the example, the source line SL is electrically connected tothe substrate 10 via the contact portion 25 and the source contact 60.Accordingly, a source potential of 3 V is applied also to the substrate10.

Then, via the row decoder 13, the controller 18 applies Vcc to theselection gate 40 d and sets the potential of the selection gate 40 s to0 (zero) V. Further, via the row decoder 13, the controller 18 appliesVpp to the word line 30 connected to the memory cell transistor MTrs.Also, via the row decoder 13, the controller 18 applies Vpass to theother word lines 30 connected to the memory cell transistors MTrn.

In the memory string MS1, the gate potential V_(GD) of the selectiontransistor STD1 is Vcc; and the potential on the drain side is 0 V.Accordingly, the selection transistor STD1 is switched to the ON state.On the other hand, the gate potential V_(GS) of the selection transistorSTS1 is 0 V; and the source potential of the selection transistor STS1is 3 V. Accordingly, the selection transistor STS1 is switched to theOFF state. The gate potentials of the memory cell transistors MTrs andMTrn are higher than the threshold voltage; and the memory celltransistors MTrs and MTrn are switched to the ON state. As a result, thechannel potential Vch1 of the memory cell transistors MTr is 0 V whichis the same as that of the bit line BL1. Then, by the programmingvoltage Vpp applied between the word line 30 and the channel of thememory cell transistor MTrs, electric charges are injected from thesemiconductor layer 20 a into the charge storage layer 21; and the datais programmed to the memory cell transistor MTrs.

In contrast, in the memory string MS2, Vcc is applied to the drain ofthe selection transistor STD2 via the bit line BL2. The selectiontransistor STD2 shares the selection gate 40 d with the selectiontransistor STD1. Accordingly, the gate potential V_(GD) is Vcc.Therefore, the selection transistor STD2 is switched to the OFF state.On the other hand, the selection transistor STS2 shares the selectiongate 40 s with the selection transistor STS1; and the gate potentialV_(GD) of the selection transistor STS2 is 0 V. A potential of 3 V isapplied to the source of the selection transistor STS2 via the sourceline SL. Accordingly, the selection transistor STS2 is switched to theOFF state. As a result, the channel potential Vch2 of the memory celltransistors MTr is the floating potential.

A potential of 3 V is applied to the substrate 10 via the source lineSL; and the substrate potential becomes 3 V. Accordingly, the channelpotential Vch2 is pushed upward to the positive side. As a result, inthe memory string MS2, the potential difference between the word line 30and the channel of the memory cell transistor MTrn becomes small; andthe damage of the tunneling insulating layer may be suppressed. Becausethe source potential supply unit 16 supplies the potential to thesubstrate 10, it is no longer necessary in this example to provide thesubstrate potential supply unit 17 in the peripheral circuit.

FIG. 4C shows the gate potentials V_(GM), V_(GD), and V_(GS), thepotential of the bit line BL, and the potential of the source line SLwhen erasing data. The controller 18 applies the erasing voltage Vera tothe source line SL via the source potential supply unit 16. On the otherhand, via the sense amplifier 15, the controller 18 sets the potentialof the bit line BL to the floating potential. Also, via the row decoder,the controller 18 sets the potentials of the selection gates 40 d and 40s to the floating potential and sets the potential of each word line 30to 0 V.

By the potential setting recited above, the gate potential V_(GD) of theselection transistor STD is set to the floating potential; and theselection transistor STD is switched to the OFF state. Also, the gatepotential V_(GS) of the selection transistor STS is set to the floatingpotential; and the source potential of the selection transistor STS isVera. Therefore, the selection transistor STS is switched to the ONstate; and the channel potential Vch of the memory cell transistors MTris Vera. As a result, Vera is applied between the word line 30 and thechannel of the memory cell transistor MTr; and the electric charges areremoved from the charge storage layer 21 into the semiconductor layer20. Thereby, the data that is stored in the memory cell transistors MTris erased.

Vera is applied to the substrate 10 via the contact portion 25.Accordingly, the substrate 10 has the same potential as thesemiconductor layer 20 when erasing data; and the damage of theinsulating layer 70 due to the electric field is avoided.

FIG. 4D shows the gate potentials V_(GM), V_(GD), and V_(GS), thepotential of the bit line BL, and the potential of the source line SLwhen reading data. FIG. 4D is a cross-sectional view of the memorystring MS including the memory cell transistor MTrs that is selected forreading the data.

As shown in FIG. 4D, the controller 18 applies Vcc to the selectiongates 40 d and 40 s via the row decoder 13. Also, via the row decoder13, the controller 18 applies Vdata to the word line 30 connected to theselected memory cell transistor MTrs and applies Vread to the word linesconnected to the unselected memory cell transistors MTrn. Then, thecontroller 18 applies Vbit to the bit line BL via the sense amplifier 15and sets the potential of the source line SL to 0 V via the sourcepotential supply unit 16. The substrate 10 has the same potential as thesource line SL.

By the potential setting recited above, the selection transistors STDand STS are switched to the ON state. The gate potential V_(GM) of theunselected memory cell transistors MTrn is Vread; and the unselectedmemory cell transistors MTrn are switched to the ON state. Then, thecontroller 18 sweeps Vdata via the row decoder 13 and senses thethreshold voltage of the memory cell transistor MTrs.

FIGS. 5A and 5B are schematic cross-sectional views showing operationsof a memory cell array 4 according to a variation of the firstembodiment. FIGS. 5A and 5B are cross-sectional views along line 1B-1Bshown in FIG. 1B. In FIGS. 5A and 5B, the insulating layers that areprovided to be higher than the semiconductor layers 20 are not shown.

As shown in FIGS. 5A and 5B, the memory cell array 4 is provided on thesubstrate 10. The memory cell array 4 includes the memory celltransistors MTr, the selection transistor STD, and the selectiontransistor STS. The memory cell array 4 further includes the insulatinglayer 70 between the substrate 10 and the semiconductor layer 20. Theinsulating layer 70 includes a first portion 70M and a second portion70S. The first portion 70M is positioned under the memory celltransistors MTr. The second portion 70S is positioned under theselection transistor STD or STS. A thickness T_(OXS) in the Z-directionof the second portion 70S is thicker than a thickness T_(OXM) in theZ-direction of the first portion 70M.

FIGS. 5A and 5B show the gate potentials V_(GM), V_(GD), and V_(GS), thepotential of the bit line BL, and the potential of the source line SLwhen programming data. FIG. 5A shows the memory string MS1; and FIG. 5Bshows the memory string MS2. The memory string MS1 includes the memorycell transistor MTrs that is selected for programming data, and thememory cell transistors MTrn that are unselected. The memory string MS2includes only the unselected memory cell transistors MTrn. The wordlines 30 and the selection gates 40 d and 40 s are shared by the memorystrings MS1 and MS2.

For example, via the sense amplifier 15, the controller 18 selects thebit line BL1 electrically connected to the memory string MS1 and setsthe potential of the bit line BL1 to 0 (zero) V. Also, via the senseamplifier 15, the controller 18 applies Vcc to the bit line BL2connected to the memory string MS2. Further, for example, a potential of2 V is applied to the source line SL via the source potential supplyunit 16.

Then, via the row decoder 13, the controller 18 applies Vcc to theselection gate 40 d and sets the potential of the selection gate 40 s to0 (zero) V. Further, via the row decoder 13, the controller 18 appliesVpp to the word line 30 connected to the memory cell transistor MTrs.Also, via the row decoder 13, the controller 18 applies Vpass to theother word lines 30 connected to the memory cell transistors MTrn.

In the memory string MS1, the selection transistor STD1 is switched tothe ON state. On the other hand, the selection transistor STS1 isswitched to the OFF state. The memory cell transistors MTrs and MTrn areswitched to the ON state. As a result, the channel potential Vch1 of thememory cell transistors MTr is 0 V which is the same as the bit lineBL1. Then, by the programming voltage Vpp applied between thegate-channel for the memory cell transistor MTrs, electric charges areinjected from the semiconductor layer 20 a into the charge storage layer21; and the data is programmed to the memory cell transistor MTrs.

In contrast, in the memory string MS2, the selection transistors STD2and STS2 are switched to the OFF state. Thus, the channel potential Vch2of the memory cell transistors MTr is the floating potential.

The controller 18 applies the potential Vsub to the substrate 10 via thesubstrate potential supply unit 17. Vsub is, for example, 3 V to 9 V.Therefore, the channel potential Vch2 is pushed upward to the positiveside. As a result, in the memory string MS2, the potential differencebetween the word line 30 and the channel of the memory cell transistorMTrn becomes small; and the damage of the tunneling insulating layer maybe suppressed.

In the example, the insulating layer 70 includes the first portion 70Mand the second portion 705. The thickness T_(OXS) of the second portion70S is thicker than the thickness T_(OXM) of the first portion 70M.Accordingly, in the memory string MS2, the unintentional change of thepotential between the selection gate 40 and the channel of the selectiontransistor STD or STS may be suppressed while maintaining the increaseof the channel potential Vch of the memory cell transistors MTr. Inother words, the operations of the selection transistors STD and STS maybe stabilized.

FIGS. 6A and 6B are schematic cross-sectional views showing operationsof a memory cell array 5 according to a variation of the firstembodiment. FIGS. 6A and 6B are cross-sectional views along line 1B-1Bshown in FIG. 1B. In FIGS. 6A and 6B, the insulating layers that areprovided to be higher than the semiconductor layers 20 are not shown.

The memory cell array 5 includes the memory cell transistors MTr and theselection transistors STD and STS provided on the semiconductor layer20. Further, the memory cell array 5 includes, for example, a p-typewell 11 provided in a top surface of the substrate 10. Also, the memorycell array includes the insulating layer 70 and STI (Shallow TrenchIsolation) 75. The insulating layer 70 is provided between the p-typewell 11 and the semiconductor layer 20. The memory cell transistors MTrare arranged on the p-type well 11 with the insulating layer 70interposed between the p-type well 11 and the memory cell transistorsMTr. The selection transistors STD and STS are provided on the STI 75.For example, the STI 75 is provided around the p-type well 11. In otherwords, the STI 75 defines the outer edge of the p-type well 11 andelectrically insulates the p-type well 11 from the other portions of thesubstrate 10. For example, the p-type well 11 is provided for eachmemory block MB.

FIGS. 6A and 6B show the gate potentials V_(GM), V_(GD), and V_(GS), thepotential of the bit line BL, and the potential of the source line SLwhen programming data. FIG. 6A shows the memory string MS1; and FIG. 6Bshows the memory string MS2. The memory string MS1 includes the memorycell transistor MTrs that is selected for programming data, and thememory cell transistors MTrn that are unselected. The memory string MS2includes only the unselected memory cell transistors MTrn. The wordlines 30 and the selection gates 40 d and 40 s are shared by the memorystrings MS1 and MS2.

For example, via the sense amplifier 15, the controller 18 selects thebit line BL1 electrically connected to the memory string MS, and setsthe potential of the bit line BL1 to 0 (zero) V. Also, via the senseamplifier 15, the controller 18 applies Vcc to the bit line BL2connected to the memory string MS2. Further, for example, a potential of2 V is applied to the source line SL via the source potential supplyunit 16. Also, a well potential Vwell is applied to the p-type well 11via the substrate potential supply unit 17. Vwell is, for example, 6 to9 V.

Then, via the row decoder 13, the controller 18 applies Vcc to theselection gate 40 d and sets the potential of the selection gate 40 s to0 (zero) V. Further, via the row decoder 13, the controller 18 appliesVpp to the word line 30 connected to the memory cell transistor MTrs.Also, via the row decoder 13, the controller 18 applies Vpass to theother word lines 30 connected to the memory cell transistors MTrn.

In the memory string MS1, the selection transistor STD1 is switched tothe ON state. On the other hand, the selection transistor STS1 isswitched to the OFF state. The memory cell transistors MTrs and MTrn areswitched to the ON state. As a result, the channel potential Vch1 of thememory cell transistors MTr becomes 0 V which is the same as the bitline BL1. Then, by the programming voltage Vpp that is applied betweenthe gate-channel for the memory cell transistor MTrs, electric chargesare injected from the semiconductor layer 20 a into the charge storagelayer 21; and the data is programmed to the memory cell transistor MTrs.

In contrast, in the memory string MS2, the selection transistors STD2and STS2 are switched to the OFF state. Then, the channel potential Vch2of the memory cell transistors MTr becomes the floating potential.Because Vwell is applied to the p-type well 11 in the example, thechannel potential Vch2 is pushed upward to the positive side. As aresult, in the memory string MS2, the potential difference between theword line 30 and the channel of the memory cell transistor MTrn becomessmall; and the damage of the tunneling insulating layer may besuppressed.

On the other hand, the potential of the p-type well 11 is not affectedon the selection transistors STD and STS because the selectiontransistors STD and STS are provided on the STI 75. In other words, theunintentional change of the potential between the selection gate 40 andeach channel of the selection transistors STD and STS is suppressed; andthe operations of the selection transistors STD and STS may bestabilized. Also, the potential Vwell of the p-type well 11 may be setto be higher than the substrate potential Vsub shown in FIGS. 5A and 5B.Accordingly, it is possible to further reduce the potential differencebetween the gate-channel for the memory cell transistors MTrn.

Further, the p-type well 11 may be preferably formed for each memoryblock MB, reducing the surface area of the p-type well 11. Thereby, itmay be possible to make the period of the voltage step-up/step-down forthe potential Vwell shorter. Also, the power consumption can be reducedcompared to the case where the step-up/step-down is performed for thepotential of the entire substrate 10.

Second Embodiment

FIG. 7 is a schematic cross-sectional view showing a memory cell array 6of a nonvolatile memory device according to a second embodiment. FIG. 7is, for example, a cross-sectional view along line 1B-1B shown in FIG.1B.

The memory cell array 6 includes a first semiconductor layer(hereinbelow, a semiconductor layer 20 p) that extends in theX-direction, a first selection gate (hereinbelow, a selection gate 40dp) that is provided on the semiconductor layer 20 p and extends in theY-direction intersecting the X-direction, a second selection gate(hereinbelow, a selection gate 40 sp) that is arranged with theselection gate 40 dp on the semiconductor layer 20 p and extends in theY-direction, and first word lines (hereinbelow, word lines 30 p) thatare arranged between the selection gate 40 dp and the selection gate 40sp and extend in the Y-direction.

A third selection gate (hereinbelow, a selection gate 40 dq) that isprovided on the side of the semiconductor layer 20 p opposite to theselection gate 40 dp and extends in the Y-direction, a fourth selectiongate (hereinbelow, a selection gate 40 sq) that is provided on the sideof the semiconductor layer 20 p opposite to the selection gate 40 sp andextends in the Y-direction, and second word lines (hereinbelow, wordlines 30 q) that are provided on the side of the semiconductor layer 20p opposite to the word line 30 p and extend in the Y-direction arefurther included. Also, a second semiconductor layer (hereinbelow, asemiconductor layer 20 q) extends in the X-direction between theselection gate 40 dq and the semiconductor layer 20 p, between the wordlines 30 q and the semiconductor layer 20 p, and between the selectiongate 40 sq and the semiconductor layer 20 q.

The memory cell array 6 further includes the insulating layer 70, firstcharge storage layers (charge storage layers 21 p), second chargestorage layers (charge storage layers 21 q), a first connecting portion(the drain contact 50), and a second connecting portion (the sourcecontact 60).

The insulating layer 70 is provided between the semiconductor layer 20 pand the semiconductor layer 20 q. The charge storage layers 21 p areprovided between the semiconductor layer 20 p and the word lines 30 p atthe portions where the semiconductor layer 20 p and the word lines 30 pcross. The charge storage layers 21 q are provided between thesemiconductor layer 20 q and the word lines 30 q at the portions wherethe semiconductor layer 20 q and the word lines 30 q cross.

The drain contact 50 extends through the insulating layer 70 andelectrically connects the semiconductor layer 20 p to the semiconductorlayer 20 q. Also, the source contact 60 extends through the insulatinglayer 70 and electrically connects the semiconductor layer 20 p to thesemiconductor layer 20 q. The semiconductor layer 20 p opposes theselection gate 40 dp, the charge storage layers 21 p, and the selectiongate 40 sp between a contact portion 20 dp electrically connected to thedrain contact 50 and a contact portion 20 sp electrically connected tothe source contact 60. Also, the semiconductor layer 20 q opposes theselection gate 40 dq, the charge storage layers 21 q, and the selectiongate 40 sq between a contact portion 20 dq electrically connected to thedrain contact 50 and a contact portion 20 sq electrically connected tothe source contact 60.

As shown in FIG. 7, the memory cell array 6 includes a foundation layer90, the semiconductor layer 20 p, the insulating layer 70, thesemiconductor layer 20 q, the bit line BL, and the source line SL. Thefoundation layer 90 is, for example, a silicon substrate.

For example, the semiconductor layers 20 p and 20 q and the bit line BLare arranged in order in the Z-direction perpendicular to a top surfaceof the foundation layer 90. For example, the semiconductor layers 20 pand 20 q and the bit line BL extend in the X-direction. The source lineSL is provided between the semiconductor layer 20 q and the bit line BLand extends in, for example, the Y-direction. The insulating layer 70 isprovided between the semiconductor layers 20 p and 20 q.

Memory cell transistors MTrp and selection transistors STDp and STSp areprovided between the semiconductor layer 20 p and the foundation layer90. Memory cell transistors MTrq and selection transistors STDq and STSqare provided between the semiconductor layer 20 q and the bit line BL.

The memory cell transistor MTrp includes a portion of the semiconductorlayer 20 p, a portion of the word line 30 p, and the charge storagelayer 21 p. The charge storage layer 21 p is provided between thesemiconductor layer 20 p and the word line 30 p. The word line 30 p isprovided between the charge storage layer 21 p and the foundation layer90 and extends in a direction, e.g., the Y-direction, intersecting theextension direction of the semiconductor layer 20 p.

The selection transistor STDp includes a portion of the semiconductorlayer 20 p, a portion of the selection gate 40 dp, and a conductivelayer 23 dp. The conductive layer 23 dp is provided between thesemiconductor layer 20 p and the selection gate 40 dp and iselectrically connected to the selection gate 40 dp.

The selection transistor STSp includes a portion of the semiconductorlayer 20 p, a portion of the selection gate 40 sp, and a conductivelayer 23 sp. The conductive layer 23 sp is provided between thesemiconductor layer 20 p and the selection gate 40 sp and iselectrically connected to the selection gate 40 sp. The conductivelayers 23 dp and 23 sp include, for example, the same material as thecharge storage layer 21 p.

The memory cell transistor MTrq includes a portion of the semiconductorlayer 20 q, a portion of the word line 30 q, and the charge storagelayer 21 q. The charge storage layer 21 q is provided between thesemiconductor layer 20 q and the word line 30 q. The word line 30 q isprovided between the charge storage layer 21 q and the bit line BL andextends in a direction, e.g., the Y-direction, intersecting theextending direction of the semiconductor layer 20 q.

The selection transistor STDq includes a portion of the semiconductorlayer 20 q, a portion of the selection gate 40 dq, and a conductivelayer 23 dq. The conductive layer 23 dq is provided between thesemiconductor layer 20 q and the selection gate 40 dq and iselectrically connected to the selection gate 40 dq.

The selection transistor STSq includes a portion of the semiconductorlayer 20 q, a portion of the selection gate 40 sq, and a conductivelayer 23 sq. The conductive layer 23 sq is provided between thesemiconductor layer 20 q and the selection gate 40 sq and iselectrically connected to the selection gate 40 sq. The conductivelayers 23 dq and 23 sq include, for example, the same material as thecharge storage layer 21 q.

The bit line BL is electrically connected to the semiconductor layers 20p and 20 q via the drain contact 50 on the drain side of the selectiontransistor STD. For example, the drain contact 50 extends through thesemiconductor layer 20 q and the insulating layer 70 and reaches thesemiconductor layer 20 p. The drain contact 50 contacts the contactportion 20 dp provided in the semiconductor layer 20 p and the contactportion 20 dq provided in the semiconductor layer 20 q.

The source line SL is electrically connected to the semiconductor layers20 p and 20 q via the source contact 60 on the source side of theselection transistor STS. For example, the source contact 60 extendsthrough the semiconductor layer 20 q and the insulating layer 70 andreaches the semiconductor layer 20 p. The source contact 60 contacts thecontact portion 20 sp provided in the semiconductor layer 20 p and thecontact portion 20 sq provided in the semiconductor layer 20 q.

An insulating layer 71 that covers the memory cell transistors MTrp andthe selection transistors STDp and STSp is provided between thesemiconductor layer 20 p and the foundation layer 90. An insulatinglayer 73 that covers the memory cell transistors MTrq and the selectiontransistors STDq and STSq is provided between the bit line BL and thesemiconductor layer 20 q.

In the example as well, the memory cell transistors MTr include theinsulating layer 27 between the semiconductor layer 20 and the chargestorage layers 21. Also, the memory cell transistors MTr include theinsulating layer 29 between the charge storage layers 21 and the wordlines 30. The selection transistors STD and STS include the insulatinglayer 27 between the semiconductor layer 20 and the conductive layers23. Also, the selection transistors STD and STS include the insulatinglayer 29 between the conductive layers 23 and the selection gates 40.The conductive layers 23 are electrically connected to the selectiongates 40 by the connecting portions 24 extending through the insulatinglayer 29.

FIGS. 8A and 8B are schematic cross-sectional views showing operationsof the memory cell array 6 according to the second embodiment. FIGS. 8Aand 8B show the gate potentials V_(GM), V_(GD), and V_(GS), thepotential of the bit line BL, and the potential of the source line SLwhen programming data.

FIG. 8A shows a cross section including the memory string MS1 and thememory string MS2; and FIG. 8B shows a cross section including a memorystring MS3 and a memory string MS4. The memory string MS1 includes amemory cell transistor MTrqs that is selected for programming data, andmemory cell transistors MTrqn that are unselected. The memory stringsMS2, MS3, and MS4 include only the unselected memory cell transistorsMTrpn and MTrqn. The word lines 30 q and the selection gates 40 dq and40 sq are shared by the memory strings MS1 and MS3. The word lines 30 pand the selection gates 40 dp and 40 sp are shared by the memory stringsMS2 and MS4.

For example, via the sense amplifier 15, the controller 18 selects thebit line BL1 electrically connected to the memory string MS1 and setsthe potential of the bit line BL1 to 0 (zero) V. Also, via the senseamplifier 15, the controller 18 applies Vcc to the bit line BL2connected to the memory string MS2. Further, for example, a potential of2 V is applied to the source line SL via the source potential supplyunit 16.

Then, via the row decoder 13, the controller 18 applies Vcc to theselection gate 40 dq and sets the potentials of the selection gates 40dp, 40 sp, and 40 sq to 0 (zero) V. Further, via the row decoder 13, thecontroller 18 applies Vpp to the word line 30 q connected to the memorycell transistor MTrqs. Also, via the row decoder 13, the controller 18applies Vpass to the other word lines 30 p and 30 q connected to thememory cell transistors MTrpn and MTrqn.

Here, there are cases where Vpp is applied to the word line 30 pconnected to the memory cell transistor MTrpn that is positioned, withthe semiconductor layers 20 p and 20 q interposed, on the side oppositeto the memory cell transistor MTrqs. In other words, the word line 30 pand the word line 30 q that oppose each other with the semiconductorlayers 20 p and 20 q interposed may be electrically connected and mayhave the same potential applied. Thereby, for example, the configurationof the row decoder 13 can be simplified.

In the memory string MS1, a selection transistor STDq1 is switched tothe ON state. On the other hand, a selection transistor STSq1 isswitched to the OFF state. Also, the memory cell transistors MTrq areswitched to the ON state. As a result, the channel potential Vch1 of thememory cell transistors MTr is 0 V which is the same as that of the bitline BL1. Then, by the programming voltage Vpp that is applied betweenthe gate-channel for the memory cell transistor MTrqs, electric chargesare injected from the semiconductor layer 20 q into the charge storagelayer 21 q; and the data is programmed to the memory cell transistorMTrqs.

In contrast, in the memory string MS2, selection transistors STDp1 andSTSp1 are switched to the OFF state. Accordingly, the channel potentialVch2 of the memory cell transistors MTrp is the floating potential. Forexample, the channel potential Vch2 is pulled upward by the potentialV_(GM) of the word line 30 p. As a result, in the memory string MS2, thepotential difference between the word line 30 p and the channel of thememory cell transistor MTrpn becomes small.

In the memory string MS3, a selection transistor STDq2 and a selectiontransistor STSq2 are switched to the OFF state. Then, the channelpotential Vch3 of the memory cell transistors MTrq is the floatingpotential. Also, in the memory string MS4, a selection transistor STDp2and a selection transistor STSp2 are switched to the OFF state. Then, achannel potential Vch4 of the memory cell transistors MTrp is thefloating potential. Further, a channel potential Vch3 and the channelpotential Vch4 act on each other and increase the potentials of eachother. Thereby, in the memory strings MS3 and 4, it is possible to setthe potential difference between the gate and channel in each of thememory cell transistors MTrp and MTrq to be small; and, for example, thedamage of the tunneling insulating layer may be suppressed in theunselected memory cell transistors MTrpn and MTrqn to which Vpp isapplied.

By providing the insulating layer 70 between the semiconductor layer 20p and the semiconductor layer 20 q in the embodiment as recited above,the potential difference between the gate and channel in the unselectedmemory cell transistors MTrpn and MTrqn is set to be small, whenprogramming data; and the damage of the tunneling insulating layer maybe suppressed. Also, in the embodiment, the substrate potential supplyunit 17 of the peripheral circuit can be omitted.

Third Embodiment

FIGS. 9A and 9B are schematic views showing a memory cell array 7according to a third embodiment. FIG. 9A is a schematic view showing across section along line 1B-1B of FIG. 1B. FIG. 9B is a perspective viewshowing the memory cell array 7.

As shown in FIG. 9A, the memory cell array 7 includes a semiconductorlayer 20, first stacked bodies (hereinbelow, stacked bodies 110), asecond stacked body (hereinbelow, a stacked body 120), and a thirdstacked body (hereinbelow, a stacked body 130). The semiconductor layer20 is provided on a substrate 10 with an insulating layer 70 interposed.The semiconductor layer 20 has a stripe configuration extending in theX-direction. The stacked bodies 110, 120, and 130 are provided on thesemiconductor layer 20. For example, the stacked body 120 and thestacked body 130 are arranged in the X-direction; and the multiplestacked bodies 110 are arranged between the stacked body 120 and thestacked body 130.

A stacked body 110 includes, for example, a charge storage layer 21, aword line 30, and a capping layer 33. The stacked body 120 includes, forexample, a conductive layer 23, a selection gate 40 d, and a cappinglayer 33. The stacked body 130 includes, for example, a conductive layer23, a selection gate 40 s, and a capping layer 33.

As shown in FIG. 9B, the semiconductor layers 20 are arranged in theY-direction. The word line 30, the selection gates 40 d and 40 s, andthe capping layer 33 extend in the Y-direction. The charge storage layer21 is provided between the semiconductor layer 20 and the word line 30at the portion where the semiconductor layer 20 and the word line 30cross. Charge storage layers 21 are separated from each other in theX-direction and the Y-direction. The conductive layer 23 is providedbetween the semiconductor layer 20 and the selection gate 40 at theportion where the semiconductor layer 20 and the selection gate 40cross. Conductive layers 23 are separated from each other in theY-direction.

The memory cell transistor MTr is provided at the portion where thesemiconductor layer 20 and the word line 30 cross and includes a portionof the semiconductor layer 20, the charge storage layer 21, and aportion of the word line 30. The selection transistor STD is provided atthe portion where the semiconductor layer 20 and the selection gate 40 dcross and includes a portion of the semiconductor layer 20, theconductive layer 23, and a portion of the selection gate 40 d. Theselection transistor STS is provided at the portion where thesemiconductor layer 20 and the selection gate 40 s cross and includes aportion of the semiconductor layer 20, another conductive layer 23, anda portion of the selection gate 40 s.

The memory cell array 7 includes the drain contacts 50 and the sourcecontact 60. The drain contacts 50 are provided on the drain side of theselection transistors STD. Each drain contact 50 is electricallyconnected to the semiconductor layer 20. The drain contact 50electrically connects the not-shown bit line BL to the semiconductorlayer 20. The source contact 60 is provided on the source side of theselection transistors STS. The source contact 60 extends in theY-direction and is electrically connected to the multiple semiconductorlayers 20.

The memory cell array 7 further includes the insulating layer 75provided in the substrate 10. The insulating layer 75 is provided underthe selection transistors STD and the drain contacts 50 and extends in,for example, the Y-direction. Also, another insulating layer 75 isprovided under the selection transistors STS and the source contact 60and extends in, for example, the Y-direction. The insulating layer 75contacts the insulating layer 70.

By providing the insulating layers 75 under the selection transistorsSTD and STS in the embodiment, the unintentional change of the potentialbetween a gate and a channel in each of the selection transistors STDand STS is suppressed, when reading data; and the operations of theselection transistors STD and STS are stabilized. In other words, theincrease of the channel potential due to the potential applied to thesubstrate 10 may be suppressed in the selection transistors STD and STS.

A method for manufacturing the memory cell array 7 according to thethird embodiment will now be described with reference to FIGS. 10A to22E. FIGS. 10A to 22E are schematic cross-sectional views showing themanufacturing processes of the memory cell array 7 in order.

As shown in FIG. 10A, the semiconductor layer 20 is provided on thesubstrate 10 with the insulating layer 70 interposed. In other words,the semiconductor layer 20 and the insulating layer 70 have an SOIstructure (Silicon on Insulator). The substrate 10 is, for example, asilicon substrate; and the insulating layer 70 is, for example, asilicon oxide layer. Also, the insulating layer 70 may be a siliconoxide layer having nitrogen added. The semiconductor layer 20 is, forexample, a silicon layer. The semiconductor layer 20 may contain, forexample, silicon in which amorphous silicon is crystallized.Silicon-germanium (SiGe) also may be used as the material of thesemiconductor layer 20.

As shown in FIG. 10B, a stacked body 100 is provided on thesemiconductor layer 20, in which the insulating layer 27, a conductivelayer 123, and the insulating layer 29 are formed in order. Theinsulating layers 27 and 29 are, for example, silicon oxide films. Forexample, the conductive layer 123 has a stacked structure including apolysilicon layer, an insulating layer, and a metal layer.

As shown in FIGS. 11A to 11C, the stacked body 100 is divided intomultiple stripes extending in the X-direction. FIG. 11A is a schematiccross-sectional view along line 11A-11A shown in FIG. 11B. FIG. 11B is aschematic cross-sectional view along line 11B-11B shown in FIG. 11A.FIG. 11C is a schematic cross-sectional view along line 11C-11C shown inFIGS. 11A and 11B. In the drawings hereinbelow, the cross sectionscorresponding to the drawings are illustrated by single dot-dash lines.

For example, the stacked body 100 is divided by making trenches 28 fromthe upper surface of the stacked body 100 to have a depth reaching theinsulating layer 70. As shown in FIG. 11B, the trenches 28 extend in theX-direction. Also, as shown in FIGS. 11B and 11C, an insulating layer 77is filled into the interior of the trenches 28. The insulating layer 77is so-called STI (Shallow Trench Isolation) and is linked to theinsulating layer 70. The insulating layer 77 is, for example, a siliconoxide layer.

As shown in FIGS. 12A and 12B, a conductive layer 125 and the cappinglayer 33 are formed on the stacked body 100 divided by the insulatinglayer 77. For example, the conductive layer 125 has a stacked structureincluding a metal oxide layer and a metal layer. The capping layer 33is, for example, a silicon oxide film or a silicon nitride film.

As shown in FIGS. 13A and 13B, slits 35 are formed to divide the stackedbody 100, the conductive layer 125, and the capping layer 33. The slits35 are provided from the upper surface of the capping layer 33 to adepth reaching the semiconductor layer 20 and the insulating layer 77and extend in the Y-direction. Thereby, the conductive layer 123 isdivided into the charge storage layers 21 and the conductive layers 23.Also, the conductive layer 125 is divided into the word lines 30 and theselection gates 40.

As shown in FIG. 13D, for example, the charge storage layers 21 and theconductive layers 23 have structures in which a polysilicon layer 101, asilicon nitride layer 103, a ruthenium (Ru) layer 105, and a hafniumoxide layer 107 are stacked in order. Also, for example, the word lines30 and the selection gates 40 have structures in which a hafnium oxidelayer 111, a tantalum oxynitride layer 113, and a tungsten layer 115 arestacked in order.

As shown in FIG. 13E, the conductive layers 23 are separated from eachother by the insulating layer 77 in the Y-direction. Similarly, thecharge storage layers 21 also are separated from each other by theinsulating layer 77 in the Y-direction. On the other hand, the selectiongates 40 extend in the Y-direction on the insulating layers 29 and 77.Similarly, the word lines 30 also extend in the Y-direction on theinsulating layers 29 and 77.

An insulating layer 79 is formed as shown in FIGS. 14A to 14D. Theinsulating layer 79 covers the capping layers 33 and is filled into theinteriors of the slits 35. The insulating layer 79 is, for example, asilicon oxide film.

As shown in FIGS. 15A to 15E, trenches 43 are formed to divide theselection gates 40. As shown in FIG. 15A, the trenches 43 are made abovethe semiconductor layers 20 from the upper surface of the insulatinglayer 79 to a depth reaching the conductive layers 23. As shown in FIG.15B, the trenches 43 are provided between the mutually-adjacentsemiconductor layers 20 from the upper surface of the insulating layer79 to a depth reaching the substrate 10. As shown in FIG. 15D, betweenthe mutually-adjacent semiconductor layers 20, the insulating layer 70and the insulating layer 77 are removed and the substrate 10 is exposedat the bottom surfaces of the trenches 43.

As shown in FIGS. 16A to 16E, after forming an insulating layer 53 thatcovers the side walls of the trenches 43, a part of the substrate 10 isremoved, which is exposed at the bottom surfaces of the trenches 43. Forexample, the insulating layer 53 covers the conductive layers 23 and theselection gates 40 exposed at the wall surfaces of the trenches 43 andprotects the conductive layers 23 and the selection gates 40 while thesubstrate 10 is removed. The insulating layer 53 is, for example, asilicon oxide layer.

For example, the insulating layer 53 that covers the upper surface ofthe insulating layer 79 and the inner surfaces of the trenches 43 isformed using ALD (Atomic Layer Deposition) or LPCVD (Low PressureChemical Vapor Deposition). Then, for example, the insulating layer 53that is deposited on the bottom surfaces of the trenches 43 is removedusing anisotropic dry etching, leaving the portions formed on the sidewalls of the trenches 43. Then, for example, the substrate 10 is removedto a prescribed depth using dry etching.

At this time, for example, at the exposed portions of the conductivelayers 23 above the semiconductor layers 20, the hafnium oxide layers107 which are the uppermost layers of the conductive layers 23 areexposed (referring to FIG. 13D). Accordingly, it is favorable for thesubstrate 10 to be removed using conditions at which hafnium oxide isetched with lower rate.

As shown in FIGS. 17A to 17E, hollows (hollows) 43 a are caused tospread by performing wet etching of the substrate 10 via the trenches43. For example, the substrate 10 is a silicon substrate having a (100)plane as a major surface. The etchant includes, for example, potassiumhydroxide (KOH). At this time, the insulating layer 53, the insulatinglayer 70, the insulating layer 77, and the conductive layers 23 thatcover the side walls of the trenches 43 are resistant to the etchant.Accordingly, only the substrate 10 is etched.

In the wet etching, for example, the etching rate of the (111) plane ofthe silicon is slower than the etching rate of the (100) plane.Therefore, the hollows 43 a are formed at the lower portions of thetrenches 43, which are surrounded by the (111) surfaces of silicon.Also, the hollows 43 a spread below the selection gates 40 positioned atthe two sides of the trenches 43. The final size of the hollows 43 a isdependent on the depth of the hollows 43 a made by the dry etching. Inother words, the hollows 43 a may be formed so as to spread into theentire region under the selection gate 40 by controlling the depth ofthe dry etching.

As shown in FIGS. 18A to 18E, an insulating layer 57 is formed in theinteriors of the hollows 43 a. The insulating layer 57 is, for example,a silicon oxide layer formed using high-density plasma CVD (HDP-CVD).The insulating layer 57 covers the inner surfaces of the hollows 43 a.Also, cavities 43 b are made in the insulating layer 57 because theinsulating layers 70 and 77 become eaves for the high-density plasmaexcited above the substrate 10. For example, the cavities 43 b arepositioned below the selection gates 40. Also, the cavities 43 b aremade under the semiconductor layers 20 below the selection gates 40. Forexample, the insulating layer 57 that is formed below the selectiongates 40 reduces the capacitive coupling between the substrate 10 andthe semiconductor layers 20. Also, the cavities 43 b further reduce thecapacitive coupling.

The insulating layer 57 is formed also on the side walls of the trenches43 and on the upper surface of the insulating layer 79. Although theinsulating layer 57 is formed on the conductive layers 23 exposed insidethe trenches 43, the thickness of the insulating layer 57 in theZ-direction is thinner than the thickness in the Z-direction of theportion of the insulating layer 57 formed on the insulating layer 79,for example, since the width in the Y-direction of the conductive layers23 is narrow.

As shown in FIGS. 19A to 19D, the conductive layers 23 are removed viathe trenches 43. For example, the insulating layer 57 that is formed onthe conductive layers 23 is selectively removed using anisotropic dryetching. Further, the conductive layers 23 that are exposed inside thetrenches 43 are selectively removed using anisotropic dry etching; andeach conductive layer 23 is divided into two portions that arepositioned at both sides of the trenches 43.

As shown in FIGS. 20A to 20E, sidewalls 63 are further formed in theinteriors of the trenches 43. For example, the sidewalls 63 are formedby forming a silicon oxide layer that covers the upper surface of theinsulating layer 57 and the inner surfaces of the trenches 43 usingLPCVD and by subsequently removing the silicon oxide layer that isformed on the upper surface of the insulating layer 57 and the bottomsurfaces of the trenches 43 by anisotropic dry etching, leaving theportions on the trench wall as the sidewalls 63.

As shown in FIGS. 21A to 21E, an insulating layer 65 is formed to fillthe interiors of the trenches 43. Also, the top surface of theinsulating layer 65 is planarized using, for example, CMP (ChemicalMechanical Polishing).

As shown in FIGS. 22A to 22E, contact holes 83 and 85 are made from thetop surface of the insulating layer 71 to a depth reaching thesemiconductor layers 20; and the drain contacts 50 and the sourcecontact 60 are formed in the interiors of the contact holes 83 and 85.Here, the insulating layers 57 and 53, the sidewalls 63 and theinsulating layer 65 are merged into the insulating layer 71 forconvenience. The the selection gates 40 d are positioned at two sides ofthe drain contacts 50. The selection gates 40 s are positioned at twosides of the source contact 60.

For example, the contact holes 83 and 85 are formed by selectivelyremoving the insulating layer 71 using RIE (Reactive Ion Etching).Further, for example, an n-type impurity is ion-implanted into thesemiconductor layers 20 exposed at the bottom surfaces of the contactholes 83 and 85; and subsequently, activating is carried out using RTA(Rapid Thermal Annealing). Thereby, the contact resistances are reducedbetween the semiconductor layers 20 and the drain contacts 50 andbetween the semiconductor layers 20 and the source contact.

As shown in FIGS. 23A to 23E, the insulating layer 75 without thecavities 43 b may be formed in the interiors of the hollows 43 a. Forexample, the structure that has no cavities 43 b can be formed byforming a silicon oxide layer in the interiors of the hollows 43 a usingLPCVD.

By providing the insulating layer 75 below the selection transistors STDand STS in the embodiment, the capacitive coupling can be reducedbetween the substrate 10 and the channels of the selection transistorsSTD and STS. Thereby, it is possible to suppress the unintentionalchange of the channel potential due to the potential applied to thesubstrate 10 when programming data; and the selection transistors STDand STS can operate stably.

FIGS. 24A to 24E are schematic cross-sectional views showing a memorycell array 8 according to a variation of the third embodiment. In thememory cell array 8, for example, the insulating layer 75 has a crosssection having a semicircular configuration or a semiellipticalconfiguration. For example, such a configuration is obtained byexpanding the hollows 43 a using CDE (Chemical Dry Etching) instead ofwet etching using KOH. In other words, the hollows 43 a that have crosssections having semicircular configurations or semiellipticalconfigurations can be made by removing the substrate 10 usingisotropical etching such as CDE. For example, the expanded width of theinsulating layer 75 positioned below the selection transistors STD andSTS may be controlled by the time of the etching using CDE.

FIGS. 25A to 25E are schematic cross-sectional views showing a memorycell array 9 according to a variation of the third embodiment. In thememory cell array 9, for example, the insulating layer 75 has a crosssection having an elliptical configuration. For example, such aconfiguration is obtained by expanding the hollows 43 a further usingCDE after the wet etching using KOH. In other words, by using CDE, theinner surfaces of the hollows 43 a surrounded with the (111) surface ofsilicon can be changed to curved surfaces. Thereby, the hollows 43 a canbe made, which have the cross sections having elliptical configurations,for example.

FIGS. 26A to 26D show the memory cell array 7 according to theembodiment and the memory cell array 5 according to the firstembodiment. FIGS. 26B and 26D show the potential distribution of aregion CA between the channel of the selection transistor STD and thechannel of the memory cell transistor MTr adjacent to the selectiontransistor STD.

The memory cell array 7 shown in FIG. 26A includes an insulating layer75 b having a thickness in the Z-direction that increases gradually inthe direction from the memory cell transistors MTr toward the selectiontransistor STD. On the other hand, in the memory cell array 5 shown inFIG. 26C, the thicknesses in the Z-direction of the insulating layers 70and 75 a between the substrate 10 and the semiconductor layers 20changes in a step configuration in the direction from the memory celltransistors MTr toward the selection transistor STD.

Accordingly, the channel potential Vch changes gradually between thememory cell transistor MTr and the selection transistor STD in thememory cell array 7 as shown in FIG. 26B. On the other hand, the channelpotential Vch changes abruptly between the memory cell transistor MTrand the selection transistor STD in the memory cell array 5 as shown inFIG. 26D.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the invention.

What is claimed is:
 1. A nonvolatile memory device, comprising: aconductive layer; a semiconductor layer extending in a first directionon the conductive layer; a first insulating layer provided between theconductive layer and the semiconductor layer; a word line extending in asecond direction on the semiconductor layer, the second directionintersecting the first direction; a charge storage layer providedbetween the semiconductor layer and the word line; and a circuitelectrically connected to the conductive layer, the circuit applying anelectric potential to the conductive layer when programming data, theelectric potential of the conductive layer having the same polarity asan electric potential of the word line.
 2. The nonvolatile memory deviceaccording to claim 1, wherein the absolute value of the electricpotential of the conductive layer is less than the absolute value of theelectric potential of the word line.
 3. The nonvolatile memory deviceaccording to claim 1, wherein the circuit applies the same electricpotential as an electric potential of the semiconductor layer to theconductive layer when erasing the data.
 4. The nonvolatile memory deviceaccording to claim 1, wherein the circuit includes a potential supplyunit, a row decoder, and a sense amplifier, the potential supply unitbeing electrically connected to the conductive layer, the row decoderbeing electrically connected to the word line, the sense amplifier beingelectrically connected to the semiconductor layer.
 5. The nonvolatilememory device according to claim 1, further comprising an interconnectelectrically connected to the conductive layer and the semiconductorlayer, the circuit applying an electric potential to the conductivelayer via the interconnect.
 6. The nonvolatile memory device accordingto claim 5, further comprising a connecting portion extending throughthe insulating layer and electrically connecting the conductive layer tothe semiconductor layer, wherein the interconnect is electricallyconnected to the conductive layer via the connecting portion; and thecircuit applies an electric potential to the conductive layer via theconnecting portion.
 7. The nonvolatile memory device according to claim1, further comprising a selection gate extending in the second directionon the semiconductor layer, wherein the insulating layer has a firstportion between the conductive layer and the word line, and a secondportion between the conductive layer and the selection gate; and athickness of the first portion in a third direction being from theconductive layer toward the word line is thinner than a thickness of thesecond portion in the third direction.
 8. The nonvolatile memory deviceaccording to claim 1, wherein the conductive layer is a semiconductorsubstrate.
 9. The nonvolatile memory device according to claim 1,further comprising: a selection gate extending in the second directionon the semiconductor layer; and a second insulating layer provided inthe conductive layer, the semiconductor layer extending between theselection gate and the second insulating layer.
 10. The nonvolatilememory device according to claim 9, wherein the second insulating layerhas a thickness in a third direction that increases as separating fromthe charge storage layer in the first direction.
 11. The nonvolatilememory device according to claim 9, wherein the second insulating layerincludes a cavity positioned under the selection gate.
 12. A nonvolatilememory device, comprising: a first semiconductor layer extending in afirst direction; a first selection gate provided on the firstsemiconductor layer, the first selection gate extending in a seconddirection intersecting the first direction; a second selection gatearranged with the first selection gate on the first semiconductor layer,the second selection gate extending in the second direction; a firstword line disposed between the first selection gate and the secondselection gate, the first word line extending in the second direction; athird selection gate provided on a side of the first semiconductor layeropposite to the first selection gate, the third selection gate extendingin the second direction; a fourth selection gate provided on a side ofthe first semiconductor layer opposite to the second selection gate, thefourth selection gate extending in the second direction; a second wordline provided on a side of the first semiconductor layer opposite to thefirst word line, the second word line extending in the second direction;a second semiconductor layer extending in the first direction betweenthe third selection gate and the first semiconductor layer, between thesecond word line and the first semiconductor layer, and between thefourth selection gate and the first semiconductor layer; an insulatinglayer provided between the first semiconductor layer and the secondsemiconductor layer; a first charge storage layer provided between thefirst semiconductor layer and the first word line; a second chargestorage layer provided between the second semiconductor layer and thesecond word line; a first connecting portion extending through theinsulating layer and electrically connecting the first semiconductorlayer to the second semiconductor layer.
 13. The nonvolatile memorydevice according to claim 12, further comprising: a second connectingportion extending through the insulating layer and electricallyconnecting the first semiconductor layer to the second semiconductorlayer, wherein the first selection gate, the first charge storage layer,and the second selection gate face the first semiconductor layer betweenthe first connecting portion and the second connecting portion; and thethird selection gate, the second charge storage layer, and the fourthselection gate face the second semiconductor layer between the firstconnecting portion and the second connecting portion.
 14. Thenonvolatile memory device according to claim 13, further comprising: afirst interconnect electrically connected to the first connectingportion; and a second interconnect electrically connected to the secondconnecting portion.
 15. The nonvolatile memory device according to claim12, wherein the first word line and the second word line areelectrically connected to each other.
 16. The nonvolatile memory deviceaccording to claim 12, further comprising: first conductive layersprovided respectively between the first semiconductor layer and thefirst selection gate and between the first semiconductor layer and thesecond selection gate, the first conductive layers including the samematerial as a material of the first charge storage layer; and secondconductive layers provided respectively between the second semiconductorlayer and the third selection gate and between the second semiconductorlayer and the fourth selection gate, the second conductive layersincluding the same material as a material of the second charge storagelayer.
 17. The nonvolatile memory device according to claim 16, whereinone of the first conductive layers is electrically connected to thefirst selection gate; the other of the first conductive layers iselectrically connected to the second selection gate; one of the secondconductive layers is electrically connected to the third selection gate;and the other of the second conductive layers is electrically connectedto the fourth selection gate.